In recent years, a synchronous memory that performs the operation synchronously with a clock signal is widely used as a main memory of a personal computer or the like. Among others, a DDR (Double Data Rate) synchronous memory needs to accurately synchronize input and output data with an external clock signal. Therefore, a DLL (Delay Locked Loop) circuit that generates an internal clock signal synchronously with the external clock signal is essential.
The DLL circuit includes a delay line that delays a clock signal, and a control unit that controls a delay amount of the delay line based on a phase of the clock signal. Because the DLL circuit needs to determine the delay amount accurately at a higher speed, both a CDL of a coarse adjustment pitch and an FDL of a fine adjustment pitch are often used (see Japanese Patent Application Laid-open Nos. H11-88153, H11-186903, and 2003-32104). This type of the DLL circuit first sets a rough delay amount using the CDL, and thereafter accurately sets the delay amount using the FDL. As a result, both high speed and accuracy can be established.
Because the synchronous memory uses a clock signal of a very high frequency in recent years, securing of an operation margin is very important. Therefore, high adjustment precision is also required in the DLL circuit. To increase the adjustment precision of the DLL circuit, making a smaller adjustment pitch of the FDL is effective. For example, at the time of adjusting the FDL with a four-bit count signal, a 16-step (=24) adjustment is possible. At the time of adjusting the FDL with a five-bit count signal, a 32-step (=25) adjustment is possible. Therefore, theoretically, adjustment precision of two times can be obtained.
However, when the adjustment pitch of the FDL is set small, the number of adjustment steps necessary to determine the delay amount is necessary by that amount. That is, at the time of performing adjustment by a linear search method of incrementing or decrementing the account signal for adjusting the FDL, when the number of bits of the count signal increases by one, the number of adjustment steps is doubled. As a result, it takes time for the adjustment.
On the other hand, when the number of bits of the account signal to adjust the FDL is increased, theoretically, the adjustment precision should become high. However, actually, adjustment precision of the theoretical value cannot be often obtained.